top_gen.sv

// Generated by SandPiper(TM) 1.9-2018/02/11-beta from Redwood EDA, LLC.
// (Installed here: /home/steve/repos/mono/sandpiper/distro.)
// Redwood EDA, LLC does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality.


`include "sandpiper_gen.vh"





//
// Signals declared top-level.
//

// For |calc$aa.
logic CALC_aa_a1;

// For |calc$aa_squared.
logic [7:0] CALC_aa_squared_a1,
            CALC_aa_squared_a2;

// For |calc$bb.
logic CALC_bb_a1;

// For |calc$bb_squared.
logic [7:0] CALC_bb_squared_a1,
            CALC_bb_squared_a2;

// For |calc$cc.
logic [4:0] CALC_cc_a3;

// For |calc$cc_squared.
logic [8:0] CALC_cc_squared_a2,
            CALC_cc_squared_a3;

// For |calc$r_aa.
logic [31:0] CALC_r_aa_a0,
             CALC_r_aa_a1;

// For |calc$r_bb.
logic [31:0] CALC_r_bb_a0,
             CALC_r_bb_a1;

// For |calc$r_valid.
logic [31:0] CALC_r_valid_a0,
             CALC_r_valid_a1;

// For |calc$valid.
logic CALC_valid_a1,
      CALC_valid_a2,
      CALC_valid_a3;


//
// Scope: |calc
//

// Clock signals.
logic clkP_CALC_valid_a2 ;
logic clkP_CALC_valid_a3 ;


generate


   //
   // Scope: |calc
   //

      // For signal $aa, which had no assignment.
      // Assign to a random value.
      // verilator lint_save
      // verilator lint_off WIDTH
      assign CALC_aa_a1 = CALC_r_aa_a1;
      // verilator lint_restore

      // For $aa_squared.
      always_ff @(posedge clkP_CALC_valid_a2) CALC_aa_squared_a2[7:0] <= CALC_aa_squared_a1[7:0];

      // For signal $bb, which had no assignment.
      // Assign to a random value.
      // verilator lint_save
      // verilator lint_off WIDTH
      assign CALC_bb_a1 = CALC_r_bb_a1;
      // verilator lint_restore

      // For $bb_squared.
      always_ff @(posedge clkP_CALC_valid_a2) CALC_bb_squared_a2[7:0] <= CALC_bb_squared_a1[7:0];

      // For $cc_squared.
      always_ff @(posedge clkP_CALC_valid_a3) CALC_cc_squared_a3[8:0] <= CALC_cc_squared_a2[8:0];

      // For random value for missing assignment.
      assign CALC_r_aa_a0[31:0] = $random() ^ {31'b0, clk};
      always_ff @(posedge clk) CALC_r_aa_a1[31:0] <= CALC_r_aa_a0[31:0];

      // For random value for missing assignment.
      assign CALC_r_bb_a0[31:0] = $random() ^ {31'b0, clk};
      always_ff @(posedge clk) CALC_r_bb_a1[31:0] <= CALC_r_bb_a0[31:0];

      // For random value for missing assignment.
      assign CALC_r_valid_a0[31:0] = $random() ^ {31'b0, clk};
      always_ff @(posedge clk) CALC_r_valid_a1[31:0] <= CALC_r_valid_a0[31:0];

      // For signal $valid, which had no assignment.
      // Assign to a random value.
      // verilator lint_save
      // verilator lint_off WIDTH
      assign CALC_valid_a1 = CALC_r_valid_a1;
      // verilator lint_restore
      always_ff @(posedge clk) CALC_valid_a2 <= CALC_valid_a1;
      always_ff @(posedge clk) CALC_valid_a3 <= CALC_valid_a2;




endgenerate



//
// Gated clocks.
//

generate



   //
   // Scope: |calc
   //

      clk_gate gen_clkP_CALC_valid_a2(clkP_CALC_valid_a2, clk, 1'b1, (CALC_valid_a1 ? 1'b1 : 1'bx), 1'b0);
      clk_gate gen_clkP_CALC_valid_a3(clkP_CALC_valid_a3, clk, 1'b1, (CALC_valid_a2 ? 1'b1 : 1'bx), 1'b0);



endgenerate



generate   // This is awkward, but we need to go into 'generate' context in the line that `includes the declarations file.

top.m4

\TLV_version 1a: tl-x.org
\SV
   // SystemVerilog module definition could go here.

\TLV  // enables TL-Verilog constructs
   |calc   // a pipeline, called "calc"
      ?$valid   // condition under which |calc transaction is valid
         
         // c = sqrt(a^2 + b^2), computed across 3 pipeline stages
         @1
            $aa_squared[7:0] = $aa * $aa;
            $bb_squared[7:0] = $bb * $bb;
         @2
            $cc_squared[8:0] = $aa_squared + $bb_squared;
         @3
            $cc[4:0] = sqrt($cc_squared);

\SV
   endmodule

top.sv

`line 2 "top.m4" 0 //_\TLV_version 1a: tl-x.org, generated by SandPiper(TM) 1.9-2018/02/11-beta
`include "sp_default.vh" //_\SV
   // SystemVerilog module definition could go here.

`include "top_gen.sv" //_\TLV  // enables TL-Verilog constructs
   //_|calc   // a pipeline, called "calc"
      //_?$valid   // condition under which |calc transaction is valid
         
         // c = sqrt(a^2 + b^2), computed across 3 pipeline stages
         //_@1
            assign CALC_aa_squared_a1[7:0] = `WHEN(CALC_valid_a1) CALC_aa_a1 * CALC_aa_a1;
            assign CALC_bb_squared_a1[7:0] = `WHEN(CALC_valid_a1) CALC_bb_a1 * CALC_bb_a1;
         //_@2
            assign CALC_cc_squared_a2[8:0] = `WHEN(CALC_valid_a2) CALC_aa_squared_a2 + CALC_bb_squared_a2;
         //_@3
            assign CALC_cc_a3[4:0] = `WHEN(CALC_valid_a3) sqrt(CALC_cc_squared_a3); endgenerate

//_\SV
   endmodule
SandPiper